The present invention pertains to integrated circuits and more particularly to the design and measurement of test structures for via/contact yield improvement in semiconductor manufacturing.
The fabrication of integrated circuits is an extremely complex process that may involve hundreds of individual operations. Basically, the process includes the diffusion of precisely predetermined amounts of dopant material into precisely predetermined areas of a silicon wafer to produce active devices such as transistors. This is typically done by forming a layer of silicon dioxide on the wafer, then utilizing a photomask and photoresist to define a pattern of areas into which diffusion is to occur through the silicon dioxide mask. Openings are then etched through the silicon dioxide layer to define the pattern of precisely sized and located openings through which diffusion will take place. After a predetermined number of such diffusion operations have been carried out to produce the desired number of transistors in the wafer, they are interconnected as required by interconnection lines. These interconnects are typically formed by deposition of an electrically conductive material which is defined into the desired interconnect pattern by a photomask, photoresist and etching process. A typical completed integrated circuit may have millions of transistors contained with a 0.1 inch by 0.1 inch silicon chip and interconnects of submicron dimensions.
The conductors which connect from one interconnect layer to another interconnect layer (either above or below the current layer) are called vias. The conductors which connect from one interconnect layer to a transistor are called contacts. Typically, a large complete integrated circuit may have anywhere from 1-10 million vias and contacts. A failure of any one of these vias or contacts usually means a complete failure of the circuit. Thus, exceptionally high yields are required for vias and contacts (usually better than 5 failures per billion vias or contacts).
Traditionally, via and contact yields are measured by fabricating test structures composed of chains of vias or contacts connected end to end in a serial fashion such as shown in FIG. 1. As shown in FIG. 1, the test structure chain, generally designated 10, comprises the series connection of interconnects 12 of one interconnect layer with interconnects 14 of another interconnect layer through vias 16. The ends 18 of the chain 10 are routed to test pads (not shown) to which test equipment for determining failures is connected. Optical inspection equipment is usually not reliable or useful especially for current process technologies. These chains need to be long enough to permit measurement of very small failure rates. Unfortunately, overly long via or contact chain cannot be measured because the resistance would be too high. Also, if there is a failure in a 1,000,000 long via chain, there is no easy way of knowing exactly which via or contact failed. Sometimes, a via chain will be tapped at multiple places to overcome some of these limitations, but this is usually only a limited solution.
The present invention comprises a test structure for localizing via and contact failures and for determining spatial failures within a die. The test structure of the present invention enables determination and modeling of the effect of neighborhood and via attributes on yield; observation and modeling of spatial or systematic failures within a die; measurement and modeling of via or metal shorts independently from via opens; and enables the use of digital testers as well as analog testers.
FIG. 1 is a schematic depiction of a traditional test structure chain comprising a series connection of interconnects of one interconnect layer with interconnects of another interconnect layer through vias.
FIG. 2 depicts a configuration of an exemplary embodiment of a test structure in accordance with the present invention.
FIGS. 3A, 3B and 3C are schematic depictions of examples of different block configurations for a passive multiplexor test structure in accordance with the present invention.
FIG. 4 is a schematic depiction of exemplary attributes used inside a bit cell to model via yield as a function of neighboring patterns and attributes of the via chain itself in accordance with the present invention.
FIG. 5A depicts an exemplary configuration of a multiplexor test structure with proximate neighboring structures; and FIG. 5B is a graphic depiction of an exemplary yield pattern by bit cell for the multiplexor test structure depicted in FIG. 5A.
FIG. 6A depicts an exemplary configuration of a multiplexor test structure substantially isolated from neighboring structures; and FIG. 6B is a graphic depiction of an exemplary yield pattern by bit cell for the multiplexor test structure depicted in FIG. 6A.
FIG. 7 is a schematic representation of a 4xc3x974 multiplexor test structure in which an erroneous current reading is made.
FIG. 8 is a schematic representation of a 4xc3x974 multiplexor test structure in which the erroneous current reading in FIG. 7 is eliminated.
FIG. 9A contains a table listing measurement vectors for parametric testing on a 4xc3x974 multiplexor of the type depicted schematically in FIG. 9B.
FIG. 10A is a schematic depiction of a measurement setup using a digital tester; and FIG. 10B depicts, in schematic form, that portion of the measurement test setup contained within the circled region of FIG. 10A.